This invention concerns a signal voltage level conversion circuit (level shifter) that converts input signals with a source signal waveform that has a narrow logical amplitude, e.g. 0.about.3 v, into output signals with a wide logical amplitude, e.g., 0.about.5 v; it also concerns an output buffer circuit.
In logic LSI using sub-micron semiconductor microfabrication processes, the power supply voltage for internal circuits is reduced to the 3-v level, such as 3 v and 3.3 v, in order to achieve greater reliability and low power consumption. During the transition from the currently dominant 5 v to the future 3 v level, the issue that confronts system design work is that of how to reconcile the signal I/O levels between 3 v units and the 5 v chips, given that the use of 5 v chips will continue in the peripheral LSI units. For example, when a signal, obtained in a 3 v circuit and having a narrow logical amplitude, is to be processed in a 5 v circuit system, a signal voltage level conversion circuit (level shifter) will be required that converts the input signal, with a 3 v narrow logic amplitude, to a 5 v logic amplitude (in the 0.about.5 v range).
A conceivable signal voltage level conversion circuit is a flip-flop circuit configuration made by linking two low-power consumption CMOS transistors, shown in FIG. 14, and by providing feedback. Specifically, the signal voltage level conversion circuit shown in FIG. 14 is switching-controlled by the CMOS inverter (1) (inverse signal generation circuit) that generates an inverted signal Vin (bar) with a narrow logical amplitude, 0.about.3 v, by use of the input signal Vin with a narrow logical amplitude, 0.about.3 v; a first MOS transistor Q1 (N-type transistor) that is switching-controlled by the input signal Vin; a second MOS transistor Q.sub.2 (N-type transistor) that is switching-controlled by the inverted signal V.sub.in (bar) and that turns on and off on a mutually exclusive basis with the first MOS transistor Q.sub.1 ; a third MOS transistor Q.sub.3 (P-type transistor) that is serially connected to the second MOS transistor Q.sub.2 and whose "on" operation is controlled by the "on" action of the first MOS transistor Q.sub.1 ; and a fourth MOS transistor Q.sub.4 (P-type transistor) that is serially connected to the first MOS transistor Q1 and whose "on" operation is controlled by the "on" action of the second MOS transistor Q2. The third and fourth MOS transistors, Q.sub.3, and Q.sub.4, compose a flip-flop (FF) (bi-stable circuit) that has mutually exclusive logical input points (nodes), N.sub.1, and N.sub.2, by means of a feedback loop. While the first MOS transistor Q.sub.1 is an electric potential transmission gate for the side that sends low-level (0 v) logic values to the node N.sub.1 by means of the input signal V.sub.in, the second MOS transistor Q.sub.2 functions as the other electric potential transmission gate that sends low-level (0 v) logic values to the node N.sub.2 by means of an inverted signal V.sub.in (bar). Both the first and fourth MOS transistors Q.sub.1 and Q.sub.4 are CMOS transistors. Their common drain is connected as node N.sub.1 to the gate electrode G of the third MOS transistor Q.sub.3. Similarly, the second and third MOS transistors Q.sub.2 and Q.sub.3 are CMOS transistors. Their common drain is connected as node N.sub.2 to the gate electrode G of the fourth MOS transistor Q.sub.4. The input signal Vin is applied to the gate electrode G of the first MOS transistor Q.sub.1, and the inverse signal V.sub.in (bar) is applied to the gate electrode G of the second MOS transistor Q.sub.2. Then, the output signal Vout is obtained from the other node N.sub.2.
When the input signal Vin reaches the high level at 3 v, the first MOS transistor Q.sub.1 is turned on. Because the inverted signal Vin (bar) is at the low level of 0 v, the second MOS transistor Q.sub.2 is off. When the first MOS transistor Q.sub.1 is turned on, the 0 v electric potential (ground potential) is transmitted to the node N.sub.1 of the flip-flop FF. Therefore, the 0 v electric potential is applied to the gate electrode G of the third MOS transistor Q.sub.3. Therefore, the third MOS transistor Q.sub.3 is turned on, and the output signal Vout of the node N.sub.2, the drain electrode for the third MOS transistor Q.sub.3, is maintained at the high level of 5 v. When this output signal Vout is at the high level, the fourth MOS transistor Q.sub.4 is off. Thus, when the input signal V.sub.in for the 3 v system is at the high level (3 v), the output signal for the 5 v system reaches the high level (5 v). On the other hand, when the input signal Vin is at the low level of 0 v, the first MOS transistor Q.sub.1 is turned off. When this happens, the inverted signal V.sub.in (bar) becomes the high level, thus causing the second MOS transistor Q.sub.2 to be turned on. When the second MOS transistor Q.sub.2 is on, an 0 v electric potential is transmitted to the node N.sub.2 of the flip-flop FF. Therefore, an 0 v electric potential is applied to the gate electrode G of the fourth MOS transistor Q.sub.4. This causes the fourth MOS transistor Q.sub.4 to be turned off and the node N.sub.1 to reach the high level. This causes the third MOS transistor Q.sub.3 to be off. Consequently, the output signal V.sub.out remains at the low level of 0 v.
However, in the configuration of a signal voltage level conversion circuit as shown in FIG. 14, when the input signal V.sub.in is at the high level, a 5 v electric potential is applied to the terminals between the MOS transistors Q.sub.2, Q.sub.3, and Q.sub.4. Similarly, when the input signal V.sub.in is at the low level, a 5 v electric potential is applied to the terminals between the MOS transistors Q.sub.1, Q.sub.3, and Q.sub.4. Therefore, the MOS transistors Q.sub.1 .about.Q.sub.4 must be able to withstand a 5 v voltage between gate and source, between gate and drain, and between gate and substrate. Thus, whereas the MOS transistors Q.sub.5 and Q.sub.6 for the CMOS inverter (1) need only to withstand a 3 v voltage level, the MOS transistors Q.sub.1 .about.Q.sub.4 break down if they are capable of withstanding only 3 v (gate insulator damage). This requires the use of additional fabrication processes to incorporate conventional 5 v-tolerant MOS transistors. This detracts from the progress of microfabrication processes. Because the semiconductor fabrication process for signal voltage level conversion circuits requires MOS transistors of different voltage tolerance capacities, this requires an increase in the number of fabrication processes and in complexity. This has hampered efforts to achieve cost reductions.
Therefore, a purpose of the present invention is to solve the above problems. One of its objectives is to provide a signal voltage level conversion circuit that can reduce the voltage tolerance requirements of all MOS (MIS) transistors in order to achieve a reduction in the number of semiconductor processes that are required. Another objective of the present invention is to provide an output buffer circuit that can be used appropriately in conjunction with the signal voltage level conversion circuit.